Aspects of the present invention relate generally to the field of circuit design and test, and more specifically to static timing analysis and simulation of electronics.
Integrated circuit (IC) design is increasingly complex, sometimes involving millions of elements, shapes or geometries, and may be facilitated with an electronic design automation (EDA) tool that allows a designer to interactively position (“place”) and connect (“route”) various shapes on the circuit. The EDA tool then creates a circuit layout containing the physical locations and dimensions of the circuit's components, interconnections, and various layers from the original design that may then be fabricated, creating the IC. The designed IC is eventually fabricated by transferring or printing the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the integrated circuit.
After or during the design and creation of an IC layout, validation, optimization, and verification operations are performed on the IC layout using a set of testing, simulation, analysis and validation tools. These operations are conventionally performed in part to detect and correct placement, connectivity, and timing errors. For example, as part of the verification, the IC layout may undergo circuit simulation and analysis where the signals between components are tested, for example using static timing analysis (STA) or gate level simulation (GLS).
STA is a method used to assess the timing of a digital circuit using software techniques and certain models that provide relevant characteristics of the circuit design. During STA, models of the expected timing of a digital circuit are created by estimating the expected delay within the circuit, for example, via the anticipated worst case signal path, without requiring a lengthy and cost prohibitive full simulation of the circuit. In conventional STA tools, the setup/hold timing slacks are computed based on conservative combinations of late and/or early launch and early and/or late capture arrival times. The conventional tools use both early and late arrival times on timing arcs that are common to both launching and capturing paths. Since having both early and late arrival times is impossible in a real circuit, the slack obtained is pessimistic and is referred to as Common Path Pessimism. In order to remove this pessimism, typical STA tools are equipped with a Common Path Pessimism Removal (CPPR) algorithm. These tools compute the pessimism arising due to the conservative estimates of the arcs in the common path and the computed pessimism is added to the computed slack to remove the pessimism effect.
During timing analysis of a design block, an Extracted Timing Model (ETM) may be used as an abstract representation of the timing of the interface paths of the block in order to isolate the information of the design block that may have an impact on other timing paths. Therefore, an ETM does not capture the timing of the paths between two flip-flops within the block, since these paths are fully contained inside the given block. When an ETM is extracted, the timing of the interface paths should be the same as if the design block was instantiated instead of the ETM when the ETM is plugged in to the circuit design. ETMs are important in the digital implementation and the sign-off flow, since the compact representation of the timing of the design block in the ETM saves runtime and memory requirements during analysis. It also helps in IP reuse, concurrent design development of different design blocks, and hiding the details of the design block in confidential or proprietary designs.
However, during extraction and modeling of the ETM of a design block, the common path pessimism is conventionally ignored such that additional and unnecessary pessimism is added into the model whenever there is a common timing path. Therefore, there exists a need in the art to develop a method for generating an ETM for a design block such that the pessimism arising due to the common path in the clock-network can be removed.